1. Field of the Invention
The present invention relates to an inspection technology in a semiconductor device manufacturing process, especially, to a technology for displaying an exposure condition in an exposure process.
2. Description of the Related Art
When a semiconductor substrate of a new type is manufactured in a manufacturing process for a semiconductor device, an operation for searching an optimal exposure condition in an exposure process, so called “conditioning operation” is executed before a product wafer is fed to a manufacturing process. A special wafer which is referred to as “focus & exposure matrix (FEM) wafer” is used for the above “conditioning operation”.
When an optimal exposure condition obtained by the “conditioning operation” is used, a resist pattern having an accuracy within an allowable range may be obtained at first. However, there is not obtained a resist pattern having an accuracy within the allowable range as time has passed. The reason is that, as time has passed, there are caused drifts in various kinds of sensors in an exposing device, changes in the exposure sensitivities of resists, variances in post exposure bake (PEB) temperatures, and the like. The above phenomenon is called process variation. That is, the optimal exposure condition is changed with time due to the process variation.
Conventionally, the dimension of a resist pattern of a wafer actually manufactured has been measured in order to verify the presence of the process variation in manufacturing processes of a product wafer. When a variation in the dimensions is observed by the dimension measurement in the manufacturing process, it is judged that there is a process variation, and exposure conditions are changed.
Japanese Patent Application Laid-Open No. 2003-173948 has disclosed a technology in which model data for linking exposure conditions with a scanning electron image is made using a feature quantity obtained from a secondary electron signal, and a deviation amount from an appropriate condition for an exposure process to be monitored by collating a feature quantity obtained from a secondary electron signal with the model data is estimated.
Moreover, Japanese Patent Application Laid-Open No. 2005-286095 has disclosed a technology in which an appropriate exposure process may be kept by measuring not only a variation in exposure amounts, but also an accurate variation in focus positions.
In Japanese Patent Application Laid-Open No. 2003-173948, the dimension of a resist pattern for an FEM wafer is measured using a scanning electron microscope for length measuring (hereinafter, called a length measuring SEM), and it is judged whether a feature quantity is appropriate. Thereby, it has not visually been judged which chip on a wafer has a normal resist pattern, or which chip does not have a normal pattern.